Career Profile
I’m a RTL design & verification engineer at Samsung Electronics(Foundry). I majored in VLSI/CAD(EDA) algorithms, especially focusing on the physical design optimization such as placement or routing. I got M.Sc and B.Sc degree from UNIST, Ulsan. My advisor is prof. Seokhyeong Kang at POSTECH, Pohang. I use C++ or python for write a program and farmiliar with using Verilog, System Verilog and Tcl script. I’m interested in physical design optimization and RTL design & verification.
Experiences
RTL design & verification / Library verification
EDA Algorithm / Physical Design Optimization
Thesis: A Metaheuristic Method for Fast Multi-Deck Legalization
Developing useful-skew implementation algorithm for CTS(Clock Tree Synthesis).
Research Topics
- VLSI Physical Design
- EDA Algorithm
- Place & Route
- Detailed Placement
Projects & Contests
OpenDP - Open Source Detailed Placement Project.
ICCAD 2017 Contest - EDA programming contest at ICCAD 2017. < Topic: Multi-Deck Legalization >
ICCAD 2015 Contest - EDA programming contest at ICCAD 2015. < Topic: Timing-Driven Detailed Placement >
Display Driver IC - Display Driver IC development project for Samsung Display. RTL verification, Testbench setup and formal verification.
XIP Cache Controller - Execute In Place Cache Controller develpment project for FCI corp. C++ simulator, and Testbench setup.
Publications
Compact Topology-aware Bus Routing for Design Regularity
IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019
Fence-Region Aware Mixed-Height Standard Cell Legalization
ACM Great Lakes Symposium on VLSI(GLSVLSI), 2019
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization
Design Automation Conference(DAC), 2017
Skew control methodology for useful-skew implementation
International SoC Design Conference(ISOCC), 2016